The approaches described in this section could be pursued but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
Sigma-Delta Modulator (SDM) based Digital-to-Analog converters (DACs) and Analog-to-Digital Converters (ADCs) are commonly used mixed signal (i.e., containing both analog and digital portions) circuits important to audio processing. Because analog circuits do not scale the same way as digital circuits with respect to the process technology, it may make sense implementing these circuits using two separate chips, with each taking advantage of its corresponding optimal process technology. The use of separate analog and digital chips may be done for other reasons as well.
The optimal interface between the analog and digital chips is at the output of the SDM, because this partitioning allows the digital chip to include the all-digital circuitry of the interpolating (in the DAC case) or decimation (in the ADC case) digital filters, while the analog circuitry is located entirely on the analog chip. Unfortunately, this means that the data rate for the interface is quite high, since the SDM output is at a highly oversampled rate.
Dynamic power consumption for binary digital signals in Complementary Metal-Oxide-Semiconductor (CMOS) circuits is linearly dependent on the capacitance of the signal nodes and linearly dependent on the transition rate of the nodes between the two voltages representing the two possible binary states, i.e. 0 and 1. When two chips are interconnected, the interconnection signals tend to have relatively high capacitances, and since the SDM data is highly oversampled, the transition rate is also high. Consequently, the interface can consume significant power. Therefore, it would be beneficial to minimize the transition rates at the interface nodes.